1. Field of the Invention
The present invention relates generally to a noise reduction filter array, and more particularly to a noise reduction filter array, in which each inductance portions is formed of two coil portions, and winding directions of the coil portions are set to be different so as to offset mutual interference, thus minimizing the generation of electromagnetic interference.
2. Description of the Prior Art
Generally, when electronic devices are operated, electromagnetic wave noises such as various types of power noises or clock pulse source noises exist within the devices. Especially, in mobile communication terminals, as power frequency becomes higher, great electromagnetic wave noise is generated.
Such electromagnetic wave noises are mutually propagated between circuits along circuit power lines or signal lines within electronic devices, thus causing incorrect operation of each device. Further, power noise or clock pulse source noise generated within an electronic device set is propagated to another electronic device set along a power supply line of the device set, thus causing interference with a normal operation of another electronic device set. On the other hand, a corresponding electronic device set can interfere with its normal operation due to noise propagated from another device. The interference phenomenon due to such electromagnetic wave noises is so called Electro-Magnetic Interference (EMI).
Therefore, for the purpose of performing normal operation of electronic devices, methods for reducing the electromagnetic wave noises must be considered in order to prevent this EMI when the devices are designed. Generally, a method for inserting a noise reduction filter between each circuit and each circuit power source of the electronic devices, or between each circuit and each clock pulse source of the electronic devices is used as a method for reducing the electromagnetic wave noises.
Recently, a noise reduction filter array has been popularized as a commonly used noise reduction filter. The noise reduction filter array is constructed in an array type such that a single chip has a plurality of noise reduction filters within it.
FIG. 1a is a schematic sectional view showing a conventional A noise reduction filter array 10. Referring to FIG. 1a, the noise reduction filter array 10 comprises two noise reduction filters 10a and 10b. The noise reduction filters 10a and 10b each has first and second ground electrode layers 12 and 13, capacitance portions 14a and 15a or 14b and 15b, and an inductance portion 17a or 17b. The first and second ground electrode layers 12 and 13 are respectively arranged at the upper and lower portions of a chip 11. The capacitance portions 14a and 15a or 14b and 15b are formed inside each of the first and second ground electrode layers 12 and 13. The inductance portion 17a or 17b is formed in a coil pattern. The first and second ground electrode layers 12 and 13 function as common electrodes shared between the noise reduction filters 10a and 10b. Further, input and output ports (not shown) of each noise reduction filter are formed on the front and back surfaces of the chip 11. The input ports formed on the front surface of the chip 11 are each connected to one end of each of the inductance portions 17a and 17b, and the capacitance portions 14a and 15a, while the output ports formed on the back surface of the chip 11 are each connected to the other end of each of the inductance portions 17a and 17b, and the capacitance portions 14b and 15b. 
In the noise reduction filter array 10, the first and second inductance portions 17a and 17b are symmetrically arranged adjacently to each other at the center portion of the chip 11, thus causing inductance coupling due to mutual inductance. In other words, crosstalk which is mutual electromagnetic interference can occur between the noise reduction filters 10a and 10b. Consequently, the noise reduction filter array is problematic in that undesirable influence is generated between the filters 10a and 10b due to the mutual interference, thus causing the incorrect operation of each noise reduction filter.
FIG. 1b is a graphic view showing the electromagnetic interference characteristics of a conventional noise reduction filter array. Referring to FIG. 1b, a full line represents characteristics of each noise reduction filter in the noise reduction filter array, and a dotted line represents the electromagnetic interference characteristics generated between the noise reduction filters. As shown with the dotted line, in the conventional noise reduction filter array, crosstalk occurs largely between the noise reduction filters. This is due to the mutual inductance generated between the filters arranged within a single chip, as described above. Therefore, such mutual inductance causes electromagnetic interference between the filters, thus deteriorating the filter characteristics of the array type noise reduction filter.
As described above, in this noise reduction filter technical field, a new noise reduction filter array has been required for effectively preventing crosstalk from occurring due to the mutual inductance between the inductance portions of respective noise reduction filters.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an, object of the present invention is to provide an noise reduction filter array, in which each inductance portions is formed of a plurality of coils, and winding directions of some of the coils are set opposite each other, so as to offset mutual interference generated between the coils of the noise reduction filters due to mutual inductance, thus minimizing electromagnetic interference.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of noise reduction filter array having a plurality of filters horizontally arranged within a single chip, each filter comprising, two inductance portions comprised of first and second coils connected vertically in the chip, a ground portion arranged over or under the inductance portion, and a capacitance portion arranged over or under the ground portion, wherein the first coil of one inductance portion is constructed to be wound in the same direction as that of the first coil of the other adjacent inductance portion, and the second coil of the one inductance portion is constructed to be wound in a direction opposite to the second coil of the other adjacent inductance portion
According to a preferred embodiment of this invention, inductance values of the first and second coils are set to be approximately the same value, such that mutual inductance generated by adjacent coils wound in opposite directions can be effectively offset.
According to another embodiment of this invention, the ground portion can be comprised of a first ground portion arranged over the inductance portion and a second ground portion under the inductance portion. In this case, preferably the capacitance portion is comprised of a first capacitance portion arranged under the first ground portion and a second capacitance portion arranged over the second ground portion.
According to still another preferred embodiment of this invention, the ground portion is arranged at one position of upper and lower portions of the chip, and the capacitance portion is comprised of a first capacitance portion arranged over the ground portion and a second capacitance portion arranged under the ground portion to be opposite the first capacitance portion, such that each noise reduction filter is formed in the shape of pi (xcfx80).
On the other hand, the ground portion is formed of a single layer shared between a plurality of noise reduction filters, such that it is provided as a c on ground electrode for a plurality of noise reduction filters.
According to the most preferred embodiment of this invention, each noise reduction filter further comprises an isolation means formed between the first and second coils to isolate the first and second coils from undesirable electromagnetic influence between the first and second coils. Preferably, such an isolation means can be a conductor layer having a via hole for connecting the first coil to the second coil.
In accordance with another aspect of the present invention, there is provided a noise reduction filter array having a plurality of filters horizontally arranged within a single chip, each filter comprising, two inductance portions, each comprised of first and second coil connected vertically within the chip, and each arranged horizontally, a ground portion arranged at at least one position over or under the inductance portions according to the arrangement direction of the inductance portions, a plurality of capacitance portions each vertically arranged over or under the ground portion in approximately the same direction as that of each of the inductance portions, and an isolation means for blocking electromagnetic influence between the first and the second coil of each of the inductance portions, wherein the first coil of one inductance portion is constructed to be wound in the same direction as that of the first coil of the other adjacent inductance portion, and the second coil of the one inductance portion is constructed to be wound in a direction opposite to the second coil of the other adjacent inductance portion.